System-5 Bus Driver Rev B (BUSDRV-B): KiCad master¶
Rev B (2026-10-19) replaces Rev A, whose boards (JLCPCB 2000765A-Y53, 2026-10-09) are scrap: Rev A was routed on four copper layers but ordered from a 2-layer zip (
../rev-a/README.md). Same circuit and placement as Rev A. - Changes: a true 2-layer board (gen/make_board.pyforces 2 copper layers), re-routed with Freerouting (258 segments on F.Cu/B.Cu, 7 vias); C1/C2 are 0.1" (2.54 mm) caps (busdrv.pretty/C025-050X050, Ken's rule); silkscreen and title say BUSDRV-B. - Checks: DRC 0 with zones refilled, 0 unconnected, schematic parity 0, ERC 0.busdrv-b-gerbers.zippassestools/check_order_zip.py(every copper layer, net and hole read back from the zip). - ORDERED from JLCPCB 2026-10-20, order 2000765A-Y56 (Ken; shown by JLCPCB as Y56-2000765A):busdrv-b-gerbers.zip, 2 layers, 1.6 mm, HASL. Not yet received or built.
A System-5 card modelled on the YACC1 bus tester. An Arduino Nano on USB drives two MCP23017 I²C expanders wired straight onto the 30-pin System-5 bus. - With the CPU card removed, it is bus master: it can read and write memory and I/O cards by running the 1802's bus cycle itself. - With the CPU in, it only monitors.
Designed 2026-10-06. Generated by gen/ from one netlist (gen/netlist.py). Edit gen/netlist.py and re-run the scripts, or edit in KiCad and drop the generator.
Circuit¶
| Part | What it does |
|---|---|
| A1 Arduino Nano | USB serial console. I²C on A4 (SDA) and A5 (SCL). D2/D3 take the expanders' INTA. D4 drives XRST (both expanders' reset). A0 reads BUS_SENSE. |
| U1 MCP23017 @ 0x20 | GPA0–6 = D0–D6, GPB0–6 = A0–A6, GPA7/GPB7 = SPARE1/SPARE2 |
| U2 MCP23017 @ 0x21 | GPA0–6 = D7, A7, TPA, TPB, -MRD, -MRW, -VMA. GPB0–6 = Q, -RESET, -INT, -EF, N0, N1, N2. GPA7/GPB7 = SPARE3/SPARE4. |
| J1 | System-5 30-pin bus. Same footprint and position as on every System-5 card. |
| J2 | SPARE1–4 (outputs only), +5V, GND, for flying leads or later the CPU card's mode lines |
| R1, R2 4.7k | I²C pull-ups, to bus +5V |
| R3 10k | XRST pull-up, to bus +5V |
| R4 10k / R5 100k | Bus +5V sense into A0 (reads about 4.5 V when the bus is up) |
| R6 470 / D1 | Bus power LED |
| C1, C2 0.1 µF / C3 10 µF | Bypass and bulk |
Design points: - Output-only pins: MCP23017 GPA7/GPB7 are output-only on current silicon (Microchip datasheet). So all 28 bus signals sit on bidirectional pins, which can be read when monitoring. The four output-only pins are the spares. - Power: - The Nano runs from its USB port; its +5V pin is not connected to the bus. - The expanders and pull-ups run from bus +5V. - So USB never feeds a powered-down System-5.
The firmware should keep D4 low and SDA/SCL released while BUS_SENSE shows the bus is off. Otherwise the Nano's pins back-feed the unpowered expanders through their protection diodes. - Bus lines: - The bus lines are connected directly, without series resistors (Ken's choice, as on YACC1). - Open-collector lines (-RESET, -INT, -EF) must only ever be driven low or left floating (firmware). - The firmware must not drive the bus with the CPU card plugged in: the 1802 drives its address lines even in reset. - At power-up and on XRST: the MCP23017 pins are inputs, so the card is quiet on the bus until the firmware decides otherwise.
Board¶
- Size and layout: 140.95 × 96.19 mm, 2 layers. The System-5 card outline and bus connector position are taken from the Memory Rev D board.
- The Nano sits on the right, with its USB socket at the card's outer edge.
- The power LED is in the standard System-5 position.
- Routing: Freerouting; 247 track segments, 7 vias. Signals 0.25 mm, +5V/GND 0.6 mm, GND pour on both sides. JLCPCB 2-layer rules.
- Checks, 2026-10-06:
- ERC: 0.
- Netlist proof: MATCH, 41/41 nets.
- DRC: 0 violations, 0 unconnected.
- Schematic parity: 0.
- Silkscreen: chip labels with function and I²C address; "R1 4.7k"-style values; spare-header pin names; title
BUSDRV-B.
Check before ordering: the Nano on female headers stands about 15–20 mm tall. Make sure that fits the card pitch in the System-5 cage, and that a USB cable can reach the card's outer edge with the card installed.
Files¶
| File | What it is |
|---|---|
busdrv-b.kicad_pro/.kicad_sch/.kicad_pcb |
The project |
busdrv.pretty/C30.kicad_mod |
System-5 bus connector footprint (from the Eagle C30 package) |
busdrv-b-gerbers.zip (and gerbers/) |
Upload to JLCPCB: 2 layers, 1.6 mm |
busdrv-b-bom.csv |
Parts list (stock KiCad footprints; all through-hole) |
busdrv-b-schematic.pdf, -placement.pdf, -render-top.png, -render-bottom.png |
Prints and pictures |
reports/ |
Netlist, DRC, ERC |
gen/netlist.py, make_schematic.py, make_board.py |
The generator: netlist → schematic → board |
To regenerate:
python3 gen/make_schematic.py
kicad-cli sch export netlist --format kicadsexpr -o reports/netlist.net busdrv-b.kicad_sch
<KiCad python> gen/make_board.py
Then route as in tools/kicad/kicad_route.py.
Firmware and host tool¶
- Firmware:
embedded/bus-driver/s5-bus-driver. It compiles for the Nano with arduino-cli and has not yet run on hardware. - Host tool:
software/busdrv/s5busdrv.py, with a simulator and tests. - Machine cycle: both run the 1802 cycle: high address byte on A0–7 with a TPA pulse, low byte, -VMA low, then -MRD (read D0–D7) or data on D0–D7 with a -MRW pulse.
Open items for this card are in BACKLOG.md.