System-5 bus backplane Rev D (S5BUS-D): KiCad master¶
A fresh backplane (2026-10-26), derived from the cards that plug in and from the board Ken built in 2009
(../rev-2009/, six 36-pin slots). Generated by gen/ from one netlist (gen/netlist.py): gen/make_schematic.py
writes the schematic, gen/make_board.py the board; Freerouting routes what the generator does not lay itself.
Not ordered. Before any order: python3 tools/preorder_check.py hardware/bus/kicad/rev-d/s5bus-d.kicad_pcb hardware/bus/kicad/rev-d/s5bus-d-gerbers.zip --layers 2 must PASS.
Ken's choices (2026-10-26)¶
| Choice | Decision |
|---|---|
| Pins per slot | 36, as 2009: a 30-pin card plugs into the middle 30 |
| Slots | 8 (CPU, memory, 6845, IO, IDE, bus driver, two spare) |
| Power | screw terminal, power LED, bulk capacitor, 0.1 µF at each slot; no regulator (as built in 2009) |
| Pull-ups | 10k on D0–D7 and on the open-collector lines -EF, -EF1–3, -PAUSE, -DMAIN; -INT and -RESET added 2026-10-31 |
| Idle states (2026-11-01) | 10k pull-downs on N0–N2, TPA, TPB and pull-ups on -VMA, -MRD, -MRW: with no master on the bus, no I/O port is selected, no strobe is active and no card drives the data lines or writes memory |
| Mounting holes | 8 × M3, four along each long edge, between slots |
| Review fixes (2026-10-26) | copper keep-outs at the holes, 2.5 mm supply feeds, a card-window bracket on each slot (below) |
| After the independent reviews (2026-10-27) | a 5 A power switch (E-Switch 100 series, right-angle), a 4 A polyfuse and a P-channel MOSFET for reverse-polarity protection, C1 in a 6.3 mm can, 1.0 mm silkscreen text, separate PTH / NPTH drill files |
The slot¶
Pins are numbered by position along the 36-pin socket (KiCad's PinSocket_1x36):
| Positions | Lines |
|---|---|
| 1–3 | -EF1, -EF2, -EF3 (the outer end; -EF3 next to +5V) |
| 4–33 | the 30-pin System-5 bus, pins 1–30 in order: +5V at 4, D0–D7 at 5–12, …, GND at 33 |
| 34–36 | -PAUSE, -DMAIN, SC0 (the 36-pin extension, docs/manual/bus.md; renamed 2026-10-30 from the 2009 drawing's -INP, -OUT, EXP) |
The 2009 board's silkscreen and this board agree. The 2009 copper wired -EF1 and -EF3 the other way round (its pin next to +5V is -EF1); no present card uses those lines. Its Eagle pin numbers also differ (31–33 for -EF1–3): this board numbers by position, so +5V is position 4, not pin 1.
Circuit¶
| Part | What |
|---|---|
| J1–J8 | the slots: 36-pin single-row 0.1" sockets on a 1.0" (25.4 mm) pitch, as 2009 |
| J9 | power in: 2-way 5.08 mm screw terminal at the left edge, wire entry facing out; pin 1 +5V, pin 2 GND |
| SW1 | power switch: E-Switch 100-series miniature toggle, SPDT, right-angle PCB mount (code M6, e.g. 100SP1T1B4M6RE; silver contacts 5 A at 28 VDC, 10 mΩ). Footprint s5bus.pretty/SW_Toggle_SPDT_E-Switch_100_M6, drawn from E-Switch's 100-series data sheet (M6-SP: terminals 4.70 mm apart, bracket legs 5.08 apart 12.70 in front, 1.85 mm holes). At the left edge between J9 and the power LED, its bracket legs 2.5 mm in from the edge, bushing and lever over it. Common (pin 2) from J9; pin 3 to F1 = ON with the lever up, towards J9 (a toggle closes the contact on the side away from its lever); pin 1 open = OFF. Labelled SW1 POWER, ON and OFF. A C&K 7101 with right-angle terminals is the usual alternative, but check its hole pattern first |
| F1 | 4 A resettable fuse (polyfuse), Bourns MF-RHT400 (4 A hold, 7.5 A trip at 23 °C; about 3.5 A hold at 40 °C), between SW1 and Q1 |
| Q1, R2 | reverse-polarity protection: Infineon IPP80P03P4L-04, a P-channel MOSFET in TO-220 (−30 V, −80 A, RDS(on) ≤ 7 mΩ at VGS −4.5 V), lying flat with its tab down (footprint TO-220-3_Horizontal_TabDown; it stands about 4.5 mm, so it clears the card in slot 1: an upright TO-220 stood about 19 mm, 10 mm from slot 1's centre line, final review 2026-10-28), no heatsink (2.5 A: under 50 mW). Bend the leads down 3.7 mm from the body; an M3 screw and nut through the tab's 3.5 mm hole holds it flat (optional). No top copper under the body (the tab is the drain) and none within 4 mm of the screw hole on either side. The symbol is KiCad's IRF9540N (same pinout); its Datasheet and Description fields name the IPP80P03P4L-04. Drain to the supply (after F1), source to the cards' +5V, gate to GND through R2 10k. With the supply the right way round the body diode lifts the source, VGS ≈ −5 V turns Q1 fully on and it drops under 20 mV; reversed, VGS ≈ 0 and the body diode is reverse-biased, so nothing reaches the cards. Its gate rating is +5 / −16 V: here the gate sees 0 to −5 V |
| C1 | 220 µF bulk, 6.3 mm can, 2.5 mm leads (a 16 V part: the common size) |
| C2–C9 | 0.1 µF, one above each slot, 0.1" leads |
| D1, R1 | power LED (left edge) and its 470 Ω |
| RN1 | 10k × 8 SIP-9 on D0–D7, common to +5V: stands in line with positions 4–12, its pins on those bus tracks |
| RN2 | 10k × 8 SIP-9 (bussed, as RN1) on -EF, -EF1, -EF2, -EF3, -PAUSE, -DMAIN, -INT, -RESET |
| RN3 | 10k × 5 SIP-6 (bussed, common to GND) on N0, N1, N2, TPA, TPB |
| RN4 | 10k × 3 SIP-4 (bussed, common to +5V) on -VMA, -MRD, -MRW |
| H1–H8 | M3 mounting holes, each with no copper within 4 mm of its centre on either side |
-INT and -RESET are pulled up here too (Ken, 2026-10-31). The CPU card has its own (R7, and the CM1232's reset output with R3), but with the CPU card out (bench tests from the bus driver, whose -RESET is open-collector) a floating -RESET held the 6845 in reset and blanked its screen. The two pull-ups in parallel are harmless.
Layout¶
- 2 layers, 238 × 114 mm. Each bus line is one straight track on the bottom, from the leftmost part on it across all eight slots; +5V and GND 1.5 mm, the rest 0.8 mm. The top is a GND pour (one piece; every GND pin reaches it).
- Supply feeds: all the cards' current comes in through J9, on locked tracks. Bottom side, 2.0 mm: J9 to SW1's common (pin 2, from the right), SW1 pin 3 to F1, F1 to Q1's drain, the last stretch on the top side (Q1's middle pin); then a 2.5 mm riser from Q1's source at x 30 into the +5V row. Top side, inside the GND pour: J9's GND down past SW1 and R1 into the slots' GND row at 2.5 mm. C1 (bulk) is beside the riser; R2 above Q1's gate; RN2 below slot 1's label, its legend on its right. J9's GND pin joins the top pour solidly (no thermal spokes). Voltage drop to slot 8 at 2.5 A (1 oz copper): F1 0.06-0.15 V (MF-RHT400: up to about 0.06 Ω after a trip), SW1 under 0.03 V, Q1 under 0.02 V, the feeds about 0.05 V and the +5V row about 0.08 V, so about 0.2-0.3 V in all. Set the supply to about 5.2 V and measure at slot 8 under load.
- Mounting holes: a 4 mm-radius keep-out (no track, no pour, both sides) around each hole, so a metal screw head, washer or standoff touches only bare board; the nearest track is 4.96 mm from a hole's centre. The board is 114 mm tall (was 112) so the bottom holes' keep-outs clear the EXP row.
- Card window: on each slot a silkscreen bracket marks positions 4–33, where a 30-pin card goes, with a filled triangle at the +5V end. A single-row socket would take a card shifted along it, or turned round (its +5V pin onto the backplane's GND).
- Component side: the cards' components face the power connector (left, towards J9; Ken, 2026-10-27). An arrow marked COMPONENT SIDE under each slot shows it.
- The power area is at the left end (Ken's board-layout rules for new boards: the power connector and LED at an edge, connectors facing out, every part labelled outside its body).
- Every slot pin is labelled on the silkscreen with its signal; each slot is labelled
Jn SLOT n. All silkscreen text is at least 1.0 mm tall with a 0.18 mm stroke (JLCPCB's minimum: 1.0 mm / 0.153 mm). - Fab files: plated and non-plated holes in separate drill files (
s5bus-d-PTH.drl,s5bus-d-NPTH.drl, the 3.2 mm mounting holes and Q1's 3.5 mm tab hole: 9 of the 349 holes); the drill maps stay ingerbers/and are left out of the zip. - To check when building: with a meter, unpowered: lever up (towards J9) should read about 0 Ω from J9's +5V screw to F1's left lead; lever down, open. Measure the cards' total draw once: F1 holds 4 A at room temperature, about 3.5 A at 40 °C.